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high voltage, latch - up proof, 8 - / 16 - channel multiplexers data sheet adg5206 / adg5207 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any pate nt or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analo g devices, inc. all rights reserved. technical support www.analog.com features latch - up proof 3. 5 pf off source capacitance o ff drain capacitance adg5206 : 64 pf adg5207 : 33 pf 0.35 pc typical c harge injection 0.0 2 na o n c hannel leakage low on resistance: 1 55 typ ical 9 v to 2 2 v dual - supply operation 9 v to 40 v single - supply operation v ss to v dd analog signal range human b ody m odel ( hbm ) esd rating adg5206 : 8 kv all pins adg5207 : 8 kv i/o port to supplies applications automatic test equipment data acquisition instrumentation avionics battery monitoring communication systems functional block dia grams figure 1. figure 2. general description the adg5206 and adg5207 are monolithic cmos analog multi p lexers comprising 16 single channels and 8 differential channels, respectively. the adg5206 switches one of sixteen inputs to a common output, as determined by the 4 - bit binary address lines, a0, a1, a2, and a 3 . the adg5207 switches one of eight differential inputs to a common differential output, as determined by the 3 - bit binary address lines, a0 , a1, and a2 . an en input on both devices enable s or disable s the device. when en is low, the device is disable d and all channels switch off. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample - and - hold applications , where low glitch and fast settling are required. fast switching speed coupled with high signal bandwidth make the se devices suitable for video signal switching. each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supplies. in the off condition, signal lev els up to the supplies are blocked. the adg5206 / adg5207 do not have v l pins; instead , an on - chip voltage generator generates the logic power supply internally . pro duct highlights 1. trenc h isolation guards a gainst latch - u p. a dielectric trench separates the p and n channel transistors t o prevent latch - up even under severe overvoltage conditions . 2. optimal switch design for low charge injection, low switch capacitance , and low leakage currents . 3. the adg5206 achieves 8 kv hbm esd specification on all external pins, while the adg5207 achieves 8 kv on the i/o port to supply pins, 2 k v on the i/o port to i/o port pins , and 8 kv on all other pins. 4. dual - supply ope ration. for applications where the analog signal is bipolar, the adg5206 / adg5207 can be operated from dual supplies of up to 2 2 v. 5. single - supply opera tion. for applications where the analog sign al is unipolar, the adg5206 / adg5207 can be operated from a single rail power supply of up to 40 v. adg5206 s1 s16 d 1-of-16 decoder a0 a1 a2 a3 en 10714-001 adg5207 s1a s8b da db s8a s1b 1-of-8 decoder a0 a1 a2 en 10714-002
adg5206/adg5207 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 gene ral description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual sup ply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 6 36 v single supply ........................................................................ 8 continuous current per channel, sx, d, or dx ..................... 10 absolute max imum ratings ......................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 typical performance characteristics ........................................... 16 test circuits ..................................................................................... 21 terminology .................................................................................... 23 applications information .............................................................. 24 tren ch isolation .......................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 5 /13 rev. 0 to rev. a added 32 - lead lfcsp ....................................................... universal changes to features section and product highlights section .......... 1 moved continuous current per channel, sx, d, or dx section, table 5 , and table 6 ......................................................................... 10 changes to table 7 ........................................................................... 1 1 changes to figure 3 ......................................................................... 1 2 changes to figure 5 ......................................................................... 1 3 changes to figure 30, figure 32 , and figure 33 .......................... 2 2 7 / 1 2 revision 0: initial version
data sheet adg5206/adg5207 rev. a | page 3 of 28 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 155 typ v s = 10 v, i s = ?1 ma; see figure 32 200 225 250 285 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels, r on 4 typ v s = 10 v, i s = ?1 ma 1 2 13 14 15 max on resistance flatness, r flat (on) 48 typ v s = 10 v, i s = ?1 ma 65 73 80 90 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.005 na typ v s = 10 v, v d = ? 1 0 v; see figure 33 0.1 0.15 0.2 0.4 na max match between channels, leakage , i s (off ) 1 0.01 0.015 na typ v s = 10 v, v d = ? 1 0 v drain off leakage, i d (off ) v s = 10 v, v d = ? 10 v; see figure 33 adg5206 0. 02 na typ 0. 1 0.2 5 0. 6 3. 3 na max adg5207 0.02 na typ 0. 1 0.2 5 0. 4 1. 7 na max match between channels, leakage , i d (off ), adg5207 o nly 0.015 0.015 na typ v s = 10 v, v d = ? 10 v channel on leakage, i d (on), i s (on) v s = v d = 10 v; see figure 34 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0. 02 na typ 0.1 0.2 0. 4 1.7 na max match between channels, leakage , i d (on), i s (on) 2 0.01 0.03 na typ v s = v d = 10 v digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 3 transition time, t transition 200 ns typ r l = 300 , c l = 35 pf 260 300 320 360 ns max v s = 10 v; see figure 35 t on (en) 180 ns typ r l = 300 , c l = 35 pf 245 260 270 285 ns max v s = 10 v; see figure 36 t off (en) 140 ns typ r l = 300 , c l = 35 pf 200 220 240 270 ns max v s = 10 v; see figure 36 break - before - make time delay, t d 85 ns typ r l = 300 , c l = 35 pf 27 ns min v s1 = v s2 = 10 v; see figure 37
adg5206/adg5207 data sheet rev. a | page 4 of 28 parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments charge injection, q inj 0.35 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 38 1.8 2 pc typ v s = 10 v, r s = 0 , c l = 1 nf off isolation ? 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 39 channel -to - channel crosstalk ? 76 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 40 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 41 adg5206 60 mhz typ adg5207 140 mhz typ insertion loss 6.4 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 41 c s (off ) 3. 5 pf typ v s = 0 v, f = 1 mhz c d (off ) adg5206 64 pf typ v s = 0 v, f = 1 mhz adg5207 33 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) adg5206 68 pf typ v s = 0 v, f = 1 mhz adg5207 36 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 the off channel leakage delta is calculated using the maximum of v s = +10 v and v d = ?10 v, or v s = ? 10 v and v d = +10 v. 2 the on channel leakage delta is calculated using the maximum of v s = v d = +10 v, or v s = v d = ? 10 v. 3 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 130 typ v s = 15 v, i s = ?1 ma; see figure 32 160 180 200 230 max v dd = +18 v, v ss = ?18 v on- resistance match between channels, ? r on 4 typ v s = 15 v, i s = ?1 ma 12 13 14 15 max on - resistance flatness, r flat (on) 35 typ v s = 15 v, i s = ?1 ma 50 58 65 75 max
data sheet adg5206/adg5207 rev. a | page 5 of 28 parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments leakage currents v dd = + 22 v, v ss = ?22 v source off leakage, i s (off ) 0.005 na typ v s = 15 v, v d = ? 15 v; see figure 33 0.1 0.15 0.2 0.4 na max match between channels, leakage, i s (off ) 1 0.01 0.015 na typ drain off leakage, i d (off ) v s = 1 5 v, v d = ? 1 5 v; see figure 33 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0.02 na typ 0.1 0.25 0.4 1.7 na max match between channels, leakage, i d (off ), adg5207 o nly 0.015 0.015 na typ channel on leakage, i d (on), i s (on) v s = v d = 1 5 v; see figure 34 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0. 02 na typ 0.1 0.2 0. 4 1.7 na max match between channels, leakage , i d (on), i s (on) 2 0.01 0.03 na typ digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 3 transition time, t transition 185 ns typ r l = 300 , c l = 35 pf 240 270 290 320 ns max v s = 10 v; see figure 35 t on (en) 175 ns typ r l = 300 , c l = 35 pf 230 245 255 270 ns max v s = 10 v; see figure 36 t off (en) 135 ns typ r l = 300 , c l = 35 pf 185 205 220 245 ns max v s = 10 v; see figure 36 break - before - make time delay, t d 75 ns typ r l = 300 , c l = 35 pf 27 ns min v s1 = v s2 = 10 v; see figure 37 charge injection, q inj 0.45 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 38 4 4 pc typ v s = 10 v, r s = 0 , c l = 1 nf off isolation ? 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 39 channel -to - channel crosstalk ? 76 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 40 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 41 adg5206 65 mhz typ adg5207 145 mhz typ insertion loss 5.6 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 41 c s (off ) 3. 3 pf typ v s = 0 v, f = 1 mhz
adg5206/adg5207 data sheet rev. a | page 6 of 28 parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments c d (off ) adg5206 62 pf typ v s = 0 v, f = 1 mhz adg5207 32 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) adg5206 67 pf typ v s = 0 v, f = 1 mhz adg5207 35 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 the off channel leakage delta is calculated using the maximum of v s = +15 v and v d = ? 15 v, or v s = ? 15 v and v d = +15 v. 2 the on channel leakage delta is calculated using the maximum of v s = v d = +15 v, or v s = v d = ? 15 v. 3 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3 . parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 350 typ v s = 0 v to 10 v, i s = ?1 ma; see figure 32 500 560 610 700 max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 5 typ v s = 0 v to 10 v, i s = ?1 ma 20 21 22 24 max on - resistance flatness, r flat (on) 170 typ v s = 0 v to 10 v, i s = ?1 ma 280 310 335 370 max leakage currents v dd = + 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.005 na typ v s = 1 v/ 10 v, v d = 1 0 v /1 v ; see figure 33 0.1 0.15 0.2 0.4 na max match between channels, leakage, i s (off ) 1 0.01 0.015 na typ drain off leakage, i d (off ) v s = 1 v/ 10 v, v d = 1 v/ 10 v; see figure 33 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0.02 na typ 0.1 0.25 0.4 1.7 na max match between channels, leakage, i d (off ), adg5207 o nly 0.015 0.015 na typ channel on leakage, i d (on), i s (on) v s = v d = 1 v/ 10 v; see figure 34 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0. 02 na typ 0.1 0.2 0. 4 1.7 na max match between channels, leakage , i d (on), i s (on) 2 0.01 0.03 na typ
data sheet adg5206/adg5207 rev. a | page 7 of 28 parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 3 transition time, t transition 290 ns typ r l = 300 , c l = 35 pf 290 440 480 550 ns max v s = 8 v; see figure 35 t on (en) 230 ns typ r l = 300 , c l = 35 pf 290 320 340 370 ns max v s = 8 v; see figure 36 t off (en) 230 ns typ r l = 300 , c l = 35 pf 315 360 390 450 ns max v s = 8 v; see figure 36 break - before - make time delay, t d 170 ns typ r l = 300 , c l = 35 pf 45 ns min v s1 = v s2 = 8 v; see figure 37 charge injection, q inj 0.25 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 38 0.6 0.7 pc typ v s = 0 v to 10 v, r s = 0 , c l = 1 nf off isolation ? 90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 39 channel -to - channel crosstalk ? 76 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 40 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 41 adg5206 50 mhz typ adg5207 105 mhz typ insertion loss 8.55 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 41 c s (off ) 3.6 pf typ v s = 6 v, f = 1 mhz c d (off ) adg5206 71 pf typ v s = 6 v, f = 1 mhz adg5207 36 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) adg5206 75 pf typ v s = 6 v, f = 1 mhz adg5207 40 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 the off channel leakage delta is calculated using the maximum of v s = 1 v and v d = 10 v, or v s = 10 v and v d = 1 v. 2 the on channel leakage delta is calculated using the maximum of v s = v d = 1 v, or v s = v d = 10 v. 3 guaranteed by design; not subject to production test.
adg5206/adg5207 data sheet rev. a | page 8 of 28 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4 . parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 140 typ v s = 0 v to 30 v, i s = ?1 ma; see figure 32 170 195 215 245 max v dd = 32.4 v, v ss = 0 v on- resistance match between channels, ? r on 4 typ v s = 0 v to 30 v, i s = ?1 ma 12 13 14 15 max on - resistance flatness, r flat (on) 40 typ v s = 0 v to 30 v, i s = ?1 ma 55 63 70 80 max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off ) 0.005 na typ v s = 1 v/ 3 0 v, v d = 3 0 v /1 v ; see figure 33 0.1 0.15 0.2 0.4 na max match between channels, leakage, i s (off ) 1 0.01 0.015 na typ drain off leakage, i d (off ) v s = 1 v/3 0 v, v d = 3 0 v /1 v ; see figure 33 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0.02 na typ 0.1 0.25 0.4 1.7 na max match between channels, leakage, i d (off ), adg5207 o nly 0.015 0.015 na typ channel on leakage, i d (on), i s (on) v s = v d = 1 v/3 0 v; see figure 34 adg5206 0. 02 na typ 0.1 0.25 0.6 3.3 na max adg5207 0. 02 na typ 0.1 0.2 0. 4 1.7 na max match between channels, leakage , i d (on), i s (on) 2 0.01 0.03 na typ digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 3 transition time, t transition 225 ns typ r l = 300 , c l = 35 pf 290 310 320 350 ns max v s = 18 v; see figure 35 t on (en) 215 ns typ r l = 300 , c l = 35 pf 265 285 285 295 ns max v s = 18 v; see figure 36 t off (en) 170 ns typ r l = 300 , c l = 35 pf 215 230 245 270 ns max v s = 18 v; see figure 36 break - before - make time delay, t d 90 ns typ r l = 300 , c l = 35 pf 28 ns min v s1 = v s2 = 18 v; see figure 37 charge injection, q inj 0.7 pc typ v s = 18 v, r s = 0 , c l = 1 nf; see figure 38 3 3 pc typ v s = 0 v to 30 v, r s = 0 , c l = 1 nf
data sheet adg5206/adg5207 rev. a | page 9 of 28 parameter 25c ? 40 c to +60c ? 40 c to +85c ? 40 c to +125c unit test conditions/comments off isolation ?90 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 39 channel -to - channel crosstalk ? 76 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 40 ?3 db bandwidth r l = 50 , c l = 5 pf; see figure 41 adg5206 55 mhz typ adg5207 115 mhz typ insertion loss 5.65 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 41 c s (off ) 3. 4 pf typ v s = 18 v, f = 1 mhz c d (off ) adg5206 62 pf typ v s = 18 v, f = 1 mhz adg5207 32 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) adg5206 66 pf typ v s = 18 v, f = 1 mhz adg5207 35 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 the off channel leakage delta is calculated using the maximum of v s = 1 v and v d = 30 v, or v s = 30 v and v d = 1 v. 2 the on channel leakage delta is calculated using the maximum of v s = v d = 1 v, or v s = v d = 30 v. 3 guaranteed by design; not subject to production test.
adg5206/adg5207 data sheet rev. a | page 10 of 28 continuous current p er channel, s x , d, or d x table 5 . adg5206 parameter 25c 60c 85c 125c unit continuous current, sx or d v dd = +15 v, v ss = ?15 v tssop ( ja = 67.7c/w) 44 32 23 12 ma maximum lfcsp ( ja = 27.27c/w) 62 42 28 13 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 67.7c/w) 47 33 24 12 ma maximum lfcsp ( ja = 27.27c/w) 66 44 29 13 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 67.7c/w) 31 24 19 11 ma maximum lfcsp ( ja = 27.27c/w) 45 33 24 12 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 67.7c/w) 46 33 24 12 ma maximum lfcsp ( ja = 27.27c/w) 65 43 28 13 ma maximum table 6 . adg5207 parameter 25c 60c 85c 125c unit continuous current, sx or dx v dd = +15 v, v ss = ?15 v tssop ( ja = 67.7c/w) 33 25 19 11 ma maximum lfcsp ( ja = 27.27c/w) 48 34 24 12 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 67.7c/w) 35 27 20 11 ma maximum lfcsp ( ja = 27.27c/w) 51 36 25 12 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 67.7c/w) 23 19 15 1 2 ma maximum lfcsp ( ja = 27.27c/w) 34 26 20 12 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 67.7c/w) 34 26 20 11 ma maximum lfcsp ( ja = 27.27c/w) 50 35 25 12 ma maximum
data sheet adg5206/adg5207 rev. a | page 11 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 7 . parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx , d, or d x pins adg5206 140 ma (pulsed at 1 ms, 10% d uty cycle maximum) adg5207 105 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s x , d, or d x pins 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 28- lead tssop (4 - layer board) 67.7c/w 32- lead lfcsp (4 - layer board ) 2 7. 2 7c/w reflow soldering peak temperature, pb free as per jedec j - std -020 hbm esd (esda/jedec js - 001 - 2011) adg5206 all pins 8 kv adg5207 i/o port to supplies 8 kv i/o port to i/o port 2 kv all other pi ns 8 kv 1 overvoltages at the a x, en, sx, d, and d x pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 and table 6 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for exte nded periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
adg5206/adg5207 data sheet rev. a | page 12 of 28 pin configurations a nd function descript ions figure 3. adg5206 pin configuration (tssop) figure 4. adg5206 pin configuration (lfcsp) table 8 . adg5206 pin function descriptions pin no. mnemonic description tssop lfcsp 1 31 v dd most positive power supply potential. 2, 3, 13 12, 13, 26, 27, 28, 30, 32 nc no connect. not internally connected. 4 1 s16 source terminal 16. this pin can be an input or an output. 5 2 s15 source terminal 15. this pin can be an input or an output. 6 3 s14 source terminal 14. this pin can be an input or an output. 7 4 s13 source terminal 13. this pin can be an input or an output. 8 5 s12 source terminal 12. this pin can be an input or an output. 9 6 s11 source terminal 11. this pin can be an input or an output. 10 7 s10 source terminal 10. this pin can be an input or an output. 11 8 s9 source terminal 9. this pin can be an input or an output. 12 9 gnd ground (0 v) reference. 14 10 a3 logic control input. 15 11 a2 logic control input. 16 14 a1 logic control input. 17 15 a0 logic control input. 18 16 en active high digital input. when this pin is low, the device is disabled and all switches are turned off. when this pin is high, the ax logic inputs determine which switch is turned on. 19 17 s1 source terminal 1. this pin can be an input or an output. 20 18 s2 source terminal 2. this pin can be an input or an output. 21 19 s3 source terminal 3. this pin can be an input or an output. 22 20 s4 source terminal 4. this pin can be an input or an output. 23 21 s5 source terminal 5. this pin can be an input or an output. 24 22 s6 source terminal 6. this pin can be an input or an output. 25 23 s7 source terminal 7. this pin can be an input or an output. 26 24 s8 source terminal 8. this pin can be an input or an output. 27 25 v ss most negative power supply potential. in single - supply applications, this pin can be connected to ground. 28 29 d drain terminal. this pin can be an input or an output. na exposed pad the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 10714-003 1 v dd 28 d 2 nc 27 v ss 3 nc 26 s8 4 s16 25 s7 5 s15 24 s6 6 s14 23 s5 7 s13 22 s4 8 s12 21 s3 9 s11 20 s2 10 s10 19 s1 11 s9 18 en 12 gnd 17 a0 13 nc 16 a1 14 a3 15 a2 adg5206 top view (not to scale) notes 1. no connect. not internally connected. 10714-004 1 s16 2 s15 3 s14 4 s13 5 s12 6 s11 7 s10 8 s9 24 s8 23 s7 22 s6 21 s5 20 s4 19 s3 18 s2 17 s1 9 gnd 10 a3 11 a2 12 nc 13 nc 14 a1 15 a0 16 en 32 nc 31 v dd 30 nc 29 d 28 nc 27 nc 26 nc 25 v ss top view (not to scale) adg5206 notes 1. no connect. not internally connected. 2. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss .
data sheet adg5206/adg5207 rev. a | page 13 of 28 table 9 . adg5206 truth table a3 a2 a1 a0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16
adg5206/adg5207 data sheet rev. a | page 14 of 28 figure 5. adg5207 pin configuration (tssop) figure 6. adg5207 pin configuration (lfcsp) table 10. adg5207 pin function descriptions pin no. mnemonic description tssop lfcsp 1 29 v dd most positive power supply potential. 2 31 db drain terminal b. this pin can be an input or an output. 3, 13, 14 11, 12, 12, 26, 28, 30, 32 nc no connect. not internally connected. 4 1 s8b source terminal 8b. this pin can be an input or an output. 5 2 s7b source terminal 7b. this pin can be an input or an output. 6 3 s6b source terminal 6b. this pin can be an input or an output. 7 4 s5b source terminal 5b. this pin can be an input or an output. 8 5 s4b source terminal 4b. this pin can be an input or an output. 9 6 s3b source terminal 3b. this pin can be an input or an output. 10 7 s2b source terminal 2b. this pin can be an input or an output. 11 8 s1b source terminal 1b. this pin can be an input or an output. 12 9 gnd ground (0 v) reference. 15 10 a2 logic control input. 16 14 a1 logic control input. 17 15 a0 logic control input. 18 16 en active high digital input. when this pin is low, the device is disabled and all switches are turned off. when this pin is high, the ax logic inputs determine which switch is turned on. 19 17 s1a source terminal 1a. this pin can be an input or an output. 20 18 s2a source terminal 2a. this pin can be an input or an output. 21 19 s3a source terminal 3a. this pin can be an input or an output. 22 20 s4a source terminal 4a. this pin can be an input or an output. 23 21 s5a source terminal 5a. this pin can be an input or an output. 24 22 s6a source terminal 6a. this pin can be an input or an output. 25 23 s7a source terminal 7a. this pin can be an input or an output. 26 24 s8a source terminal 8a. this pin can be an input or an output. 27 25 v ss most negative power supply potential. in single - supply applications, this pin can be connected to ground. 28 27 da drain terminal a. this pin can be an input or an output. na exposed pad the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 1 v dd 28 da 2 db 27 v ss 3 nc 26 s8a 4 s8b 25 s7a 5 s7b 24 s6a 6 s6b 23 s5a 7 s5b 22 s4a 8 s4b 21 s3a 9 s3b 20 s2a 10 s2b 19 s1a 11 s1b 18 en 12 gnd 17 a0 13 nc 16 a1 14 nc 15 a2 adg5207 top view (not to scale) notes 1. no connect. not internally connected. 10714-005 10714-006 1 s8b 2 s7b 3 s6b 4 s5b 5 s4b 6 s3b 7 s2b 8 s1b 24 s8a 23 s7a 22 s6a 21 s5a 20 s4a 19 s3a 18 s2a 17 s1a 9 gnd 10 a2 11 nc 12 nc 13 nc 14 a1 15 a0 16 en 32 nc 31 db 30 v dd 29 nc 28 nc 27 da 26 nc 25 v ss top view (not to scale) adg5207 notes 1. no connect. not internally connected. 2. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss .
data sheet adg5206/adg5207 rev. a | page 15 of 28 table 11. adg5207 truth table a2 a1 a0 en on switch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8
adg5206/adg5207 data sheet rev. a | page 16 of 28 typical performance characteristics figure 7. r on as a function of v s , v d ( 20 v dual supply ) figure 8. r on as a function of v s , v d ( 15 v dual supply) figure 9. r on as a function of v s , v d ( 12 v single supply) figure 10 . r on as a function of v s , v d ( 36 v single supply) figure 11 . r on as a function of v s , v d for different temperatures, 15 v dual supply figure 12 . r on as a function of v s , v d for different temperatures, 20 v dual supply ?22.0 5.5 0 ?5.5 16.5 ?16.5 11.0 ?11.0 22.0 on resistance (?) v s , v d (v) 60 70 80 90 100 110 120 130 140 18v 20v 22v 10714-105 t a = 25c ?17.00 ?8.50 ?12.75 12.75 ?4.25 4.25 0 8.50 17.0 on resistance (?) v s , v d (v) 60 70 80 90 100 110 120 130 160 150 140 13.5v 15v 16.5v 10714-106 t a = 25c 0 2 4 6 8 10 12 on resistance (?) v s , v d (v) 60 110 160 210 260 310 360 10.8v 12v 13.2v 10714-107 t a = 25c on resistance (?) v s , v d (v) 60 70 80 90 100 110 120 130 140 150 10714-108 0 5 10 15 20 25 30 35 32.4v 36v 39.6v t a = 25c ?15 ?10 ?5 0 5 10 15 on resistance (?) v s , v d (v) 60 200 180 160 140 120 100 80 +125c +85c +60c +25c ?40c 10714-109 v dd = +15v v ss = ?15v ?20 ?15 ?10 ?5 0 5 10 20 15 on resistance (?) v s , v d (v) 60 70 80 90 100 110 120 130 140 150 160 +125c +85c +60c +25c ?40c 10714- 1 10 v dd = +20v v ss = ?20v
data sheet adg5206/adg5207 rev. a | page 17 of 28 figure 13 . r on as a function of v s , v d for different temperatures, 12 v single supply figure 14 . r on as a function of v s , v d for different temperatures, 36 v single supply figure 15 . leakage currents vs. temperature, 15 v dual supply figure 16 . leakage currents vs. temperature, 20 v dual supply figure 17 . leakage currents vs. temperature, 12 v single supply figure 18 . leakage currents vs. temperature, 36 v single supply 0 12 10 8 6 4 2 on resistance (?) v s , v d (v) 60 410 360 310 260 210 160 110 +125c +85c +60c +25c ?40c 10714- 11 1 v dd = 12v v ss = 0v 0 35 30 25 20 15 10 5 on resistance (?) v s , v d (v) 60 180 160 140 120 100 80 +125c +85c +60c +25c ?40c 10714- 1 12 v dd = 36v v ss = 0v 0 120 100 80 60 40 20 leakage current (pa) temperature (c) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i s , i d (on) + + i s , i d (on) ? ? 10714- 1 13 v dd = +15v v ss = ?15v v bias = +10v/?10v 0 120 100 80 60 40 20 leakage current (pa) temperature (c) ?300 ?250 ?200 ?150 ?100 ?50 0 50 100 150 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i s , i d (on) + + i s , i d (on) ? ? 10714- 1 14 v dd = +20v v ss = ?20v v bias = +15v/?15v 0 120 100 80 60 40 20 leakage current (pa) temperature (c) ?450 ?400 ?350 ?300 ?250 ?200 ?150 ?100 ?50 0 50 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i s , i d (on) + + i s , i d (on) ? ? 10714- 1 15 v dd = 12v v ss = 0v v bias = 1v/10v 0 120 100 80 60 40 20 leakage current (pa) temperature (c) ?350 ?300 ?250 ?200 ?150 ?100 ?50 0 50 100 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i s , i d (on) + + i s , i d (on) ? ? 10714- 1 16 v dd = 36v v ss = 0v v bias = 1v/30v
adg5206/adg5207 data sheet rev. a | page 18 of 28 figure 19 . off isolation vs. frequency, 15 v dual supply figure 20 . crosstalk vs. frequency, 15 v dual supply figure 21 . charge injection vs. source voltage , drain to source figure 22 . acpsrr vs. frequency, 15 v dual supply figure 23 . bandwidth figure 24 . charge injection vs. source voltage , source to drain 10k 1g 100m 10m 1m 100k off isolation (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 adg5206 adg5207 10714- 1 17 t a = 25c v dd = +15v v ss = ?15v 10k 1g 100m 10m 1m 100k crosstalk (db) frequency (hz) ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10714-118 between s1a and s2a between s16 and s1 between s1a and s8b t a = 25c v dd = +15v v ss = ?15v ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) 0 5 10 15 20 25 30 35 40 45 v dd = +15v, v ss = ?15v v dd = +20v, v ss = ?20v v dd = +12v, v ss = 0v v dd = +36v, v ss = 0v 10714- 1 19 t a = 25c demux (drain to source) 1k 10m 1m 100k 10k acpsrr (db) frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 decoupling capacitors no decoupling capacitors 10714-120 t a = 25c v dd = +15v v ss = ?15v 100k 1g 100m 10m 1m attenuation (db) frequency (hz) ?15 ?14 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 adg5206 adg5207 10714-121 t a = 25c v dd = +15v v ss = ?15v ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) ?2 ?1 0 1 2 3 4 5 6 7 8 v dd = +15v, v ss = ?15v v dd = +20v, v ss = ?20v v dd = +12v, v ss = 0v v dd = +36v, v ss = 0v 10714-122 t a = 25c mux (source to drain)
data sheet adg5206/adg5207 rev. a | page 19 of 28 figure 25 . q in j as a function of v s for different temperatures, 15 v dual supply figure 26 . q inj as a function of v s for different temperatures, 20 v dual supply figure 27 . t transition time vs. temperature figure 28 . q inj as a function of v s for different temperatures, 12 v single supply figure 29 . q inj as a function of v s for different temperatures, 36 v single supply ?10 10 6 2 ?2 ?6 ?8 8 4 0 ?4 charge injection (pc) v s (v) ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 10714-200 ?40c +25c +85c +125c mux (source to drain) ?15 15 0 ?5 ?10 5 10 charge injection (pc) v s (v) ?2 ?1 0 1 2 3 4 5 6 10714-201 ?40c +25c +85c +125c mux (source to drain) ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) 0 450 400 350 300 250 200 150 100 50 v dd = +12v, v ss = 0v v dd = +36v, v ss = 0v v dd = +15v, v ss = ?15v v dd = +20v, v ss = ?20v 10714-123 0 10 9 8 7 6 5 4 3 2 1 charge injection (pc) v s (v) ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10714-202 ?40c +25c +85c +125c mux (source to drain) 0 30 25 20 15 10 5 charge injection (pc) v s (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 10714-203 ?40c +25c +85c +125c mux (source to drain)
adg5206/adg5207 data sheet rev. a | page 20 of 28 figure 30 . adg520 6 capacitance vs. source voltage, 15 v dual supply figure 31 . adg520 7 capacitance vs. source voltage, 15 v dual supply ?15 ?10 ?5 0 5 10 15 capacitance (pf) v s (v) 0 100 80 60 40 20 drain off source off source/drain on 10714-124 t a = 25c v dd = +15v v ss = ?15v ?15 ?10 ?5 0 5 10 15 capacitance (pf) v s (v) 0 60 50 40 30 20 10 drain off source off source/drain on 10714-125 t a = 25c v dd = +15v v ss = ?15v
data sheet adg5206/adg5207 rev. a | page 21 of 28 test circuits figure 32 . on resistance figure 33 . off leakage figure 34 . on leakage figure 35 . address to output switching times, t transition figure 36 . enable delay, t on (en), t off (en) 10714-300 i ds s d v s v r on = v/i ds 10714-301 s1 d a a s16 a i d (off) i s (off) v s v d 10714-302 s2 s16 s1 a d nc nc = no connect i d (on) v d v d 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output adg5206 1 50? 300? gnd s1 s2 s3 to s16 d 35pf v in 3v en v dd v ss v dd v ss v s 1 similar connection for adg5207. a0 a2 a1 a3 0v 10714-034 output adg5206 1 a0 a1 a2 50? 300? gnd s1 s2 to s16 d 35pf v in en v dd v ss v dd v ss v s 3v 0v 0v output 50% 50% t off (en) t on (en) 0.9v out 0.1v out enable drive (v in ) 1 similar connection for adg5207. a3 10714-036
adg5206/adg5207 data sheet rev. a | page 22 of 28 figure 37 . break - before - make time delay, t d figure 38 . charge injection figure 39 . off isolation figure 40 . channel - to - channel crosstalk figure 41 . bandwidth 3v 0v output 80% 80% address drive (v in ) t bbm output adg5206 1 50? 300? gnd s1 s2 to s15 s16 d 35pf v in 3v en v dd v ss v dd v ss v s 1 similar connection for adg5207. a0 a2 a1 a3 10714-035 3v v in v out q inj = c l v out v out d sx en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 a3 adg5206 1 1 similar connection for adg5207. 0v 10714-037 v out 50? network analyzer r l 50? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? off isolation = 20 log v out v s 10714-032 channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 10714-030 v out 50? network analyzer r l 50? sx d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 10714-033
data sheet adg5206/adg5207 rev. a | page 23 of 28 terminology i dd i dd represents the positive supply current. i ss i ss represents th e negative supply current. v d , v s v d and v s represent the analog voltage on terminal d and terminal s, respectively. r on r on is the ohmic resistance between terminal d and terminal s. ? r on ? r on represents the difference between the r on of any two channels. r flat (on) r flat (on) is the f latness defined as the difference between the maximum and the minimum value of on resistance measured over the specified analog signal range . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum inp ut voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in represents digital input capacitance. t on (en) t on (en) represents the delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) t off (en) represents the delay time between the 50% and 90% points of the digital input and switch off condition. t transition t transition represents the d elay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. break - before - make time delay ( t d ) t d represents the off time measured between the 80% point of both switches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off channel. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is the frequency at which the output is attenuated by 3 db. on response on response is the frequency response of the on switch . ac power supply rejection ratio (acpsrr) acpsrr is a measure of the ability of a device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wa ve of 0.62 v p - p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
adg5206/adg5207 data sheet rev. a | page 24 of 28 applications informa tion the adg5 2 xx family of switches and multiplexers provide s a robust solution for instrumentation, i ndustrial, automotive, aerospace , and other harsh environments that are prone to latch - up, which is an undesirable high current state that can lead to device failure and persist until t he power supply is turned off. the adg5206 / adg5207 high voltage switches allow single - supply operation from 9 v to 40 v and dual - supply operation from 9 v to 22 v. trench isolation in the adg5206 / adg5207 , an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occu r between the transistors in junction isolated switches, are eliminated, and the result is a completely latch - up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltage conditions, this diode can become forward - biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch - up. with trench isolation, this diode is removed and the result is a latch - up proof switch. figure 42 . trench isolation nmos pmos p well n well buried oxide layer handle wafer trench 10714-038
data sheet adg5206/adg5207 rev. a | page 25 of 28 outline dimensio ns figure 43 . 28 - lead thin shrink small outline package [tssop] (ru - 28) dimensions shown in millimeters figure 44 . 32 - lead lead frame chip scale package [lfcsp_wq] 5 5 m m body, very very thin quad ( cp - 32 - 12 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5 2 06bruz ?40c to +125c 28 - lead thin shrink small outline package [tssop] ru -28 adg5 2 06bruz -rl7 ?40c to +125c 28 - lead thin shrink small outline package [tssop] ru -28 adg5206bcpz -rl7 ?40c to +125c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -12 adg5 2 07bruz ?40c to +125c 28 - lead thin shrink small outline package [tssop] ru -28 adg5 2 07bruz -rl7 ?40c to +125c 28 - lead thin shrink small outline package [tssop] ru -28 adg5207bcpz -rl7 ?40c to +125c 32 - lead lead frame chip scale package [lfcsp_wq] cp -32 -12 1 z = rohs compliant part. compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 08-16-2010-b 1 0.50 bsc b o t t o m v i e w t o p v i e w pin 1 indica t or 3 2 9 1 6 1 7 2 4 2 5 8 e x p o s e d p a d pin 1 indica t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220-whhd-5 with exception to exposed pad dimension.
adg5206/adg5207 data sheet rev. a | page 26 of 28 notes
data sheet adg5206/adg5207 rev. a | page 27 of 28 notes
adg5206/adg5207 data sheet rev. a | page 28 of 28 notes ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10714 - 0 - 5/13(a)

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